Altera FPGA



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Saint Nation Co.,Ltd. specializes in manufacturer, supplier and exporter Altera FPGA, with a factory in Taiwan. It takes science and technology innovates as the power of enterprise development. It has bend himself to the research, exploitation and production of new produce constantly. and our enterprise is long-term production supplier for many international famous companies.
  • Complex Programmable Logic Device - EPM570T144C5N
    EPM570T144C5N : Complex Programmable Logic Device
    CPLD
    1. The MAX® II family of instant-on, non-volatile CPLDs
    2. Description: The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits.
    3. Features:
      • Low-cost, low-power CPLD
      • Instant-on, non-volatile architecture
      • Standby current as low as 25 µA
      • Provides fast propagation delay and clock-to-output times
      • Provides four global clocks with two clocks available per logic array block (LAB)
      • UFM block up to 8 Kbits for non-volatile storage
      • MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V
      • MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
    4. Delivery time: 2WEEKS from distributor
    5. Payment: T/T in advance
  • Complex Programmable Logic Devices - EPM1270T144C5N
    EPM1270T144C5N : Complex Programmable Logic Devices
    CPLD
    1. The MAX® II family of instant-on, non-volatile CPLDs
    2. Description: MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP).
    3. Features:
      • Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
      • Schmitt triggers enabling noise tolerant inputs (programmable per pin)
      • I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI
      • Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
      • Supports hot-socketing
      • Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
    4. Delivery time: 2WEEKS from distributor
    5. Payment: T/T in advance
  • Field Programmable Gate Array - EP3C16F484C7N
    EP3C16F484C7N : Field Programmable Gate Array
    FPGA
    1. FPGAs
    2. Description:
      When Cyclone III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Cyclone III devices, system designers must consider the operating requirements in this document.
      Cyclone III devices are offered in commercial, industrial, and automotive grades. Commercial devices are offered in –6 (fastest), –7, and –8 speed grades.
      Industrial and automotive devices are offered only in –7 speed grade.
    3. Delivery time: 5-7days from distributor
    4. Payment: T/T in advance
  • Field Programmable Gate Arrays - EP2C35F672C6N
    EP2C35F672C6N : Field Programmable Gate Arrays
    FPGA
    1. Cyclone II FPGAs
    2. Description:
      Like Altera's highly successful first-generation 130-nm Cyclone® FPGA family, 90-nm Cyclone II FPGAs are built from the ground up for low cost and to provide a customer-defined feature set for high-volume, cost-sensitive applications. Cyclone II FPGAs deliver high performance and low power consumption at a cost that rivals that of ASICs.
      Cyclone II FPGAs are supported by the easy-to-use and free Quartus® II Web Edition design software (no license required), a broad catalog of intellectual property (IP), and hardware development kits to enable rapid development of low-cost FPGA solutions.
    3. Delivery time: 5-7days from distributor
    4. Payment: T/T in advance
  • Cyclone FPGA - EP1C3T144C8N
    EP1C3T144C8N : Cyclone FPGA
    FPGA
    1. Cyclone FPGA  
    2. Description: The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process.
    3. Features:
      • 2,910 to 20,060 LEs, see Table 1–1
      • Up to 294,912 RAM bits (36,864 bytes)
      • Supports configuration through low-cost serial configuration device
      • Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
      • Support for 66- and 33-MHz, 64- and 32-bit PCI standard
      • High-speed (640 Mbps) LVDS I/O support
      • Low-speed (311 Mbps) LVDS I/O support
      • 311-Mbps RSDS I/O support
      • Up to two PLLs per device provide clock multiplication and phase shifting
      • Up to eight global clock lines with six clock resources available per logic array block (LAB) row
      • Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
  • Altera CPLD - EPM7128STC100-7N
    EPM7128STC100-7N : Altera CPLD
    CPLD
    1. Programmable Logic Device Family
    2. Description: The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture.
    3. Features:
      • High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
      • 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532
      • Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
      • Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
      • Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
      • 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
      • PCI-compliant devices available
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
  • Programmable Logic Devices - EPM7256AETC100-7N
    EPM7256AETC100-7N : Programmable Logic Devices
    CPLD
    1. Programmable Logic Device Family
    2. Description: MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture.
    3. Features:
      • Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
      • Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
      • Enhanced ISP features
      • – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
        – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
        – Pull-up resistor on I/O pins during in-system programming
      • Pin-compatible with the popular 5.0-V MAX 7000S devices
      • High-density PLDs ranging from 600 to 10,000 usable gates
      • Extended temperature range
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
  • FPGA IC - EP1C12Q240C8N
    EP1C12Q240C8N : FPGA IC
    FPGA
    1. Cyclone FPGA Family
    2. Description: The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.
    3. Features:
      • Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
      • Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
  • CPLD IC - EP2SGX60EF1152C4N
    EP2SGX60EF1152C4N : CPLD IC
    FPGA
    1. Cyclone FPGA Family
    2. Description: Stratix II GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (CRU) technology and embedded SERDES capability at data rates of up to 6.375 gigabits per second (Gbps).
    3. Features:
      ■ Main device features:
      • TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 550 MHz
      • Up to 16 global clock networks with up to 32 regional clock networks per device region
      • High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
      • Up to four enhanced PLLs per device provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting
      • Support for numerous single-ended and differential I/O standards
      • High-speed source-synchronous differential I/O support on up to 71 channels.
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
  • Altera IC - EPM7192SQC160-7N
    EPM7192SQC160-7N : Altera IC
    CPLD
    1. Programmable Logic Device Family
    2. Description: The EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz..
    3. Features:
      • Open-drain output option in MAX 7000S devices
      • Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
      • Programmable power-saving mode for a reduction of over 50% in each macrocell
      • Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
      • 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
      • Programmable security bit for protection of proprietary designs
      • 3.3-V or 5.0-V operation – MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
  • Stratix II FPGA - EP2SGX60EF1152C5N
    EP2SGX60EF1152C5N : Stratix II FPGA
    FPGA
    1. Stratix II FPGA Family
    2. Description: All Stratix II GX devices support vertical migration within the same package.
    3. Features:
      • High-speed serial transceiver channels with clock data recovery (CDR) provide 600-megabits per second (Mbps) to 6.375-Gbps full-duplex transceiver operation per channel
      • Devices available with 4, 8, 12, 16, or 20 high-speed serial transceiver channels providing up to 255 Gbps of serial bandwidth (full duplex)
      • Dynamically programmable voltage output differential (VOD) and pre-emphasis settings for improved signal integrity
      • Support for CDR-based serial protocols, including PCI Express, Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, CEI-6G, CPRI, Serial RapidIO, SONET/SDH
      • Dynamic reconfiguration of transceiver channels to switch between multiple protocols and data rates
      • Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
      • Adaptive equalization (AEQ) capability at the receiver to compensate for changing link characteristics.
    4. Delivery time: 5-7days from distributor
    5. Payment: T/T in advance
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Altera FPGA

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